1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device including a driver.
2. Description of the Related Art
A semiconductor memory device generally has a hierarchical line structure. In other words, memory cells are coupled with bit lines (BL), and the bit lines (BL) are coupled with local input/output (LIO) lines, and the local input/output (LIO) lines are coupled with global input/output (GIO) lines. These lines have to be developed to transfer data based on a read or write command and to be precharged before the next read or write command is applied.
The current that is consumed during read/write operations of the semiconductor memory device is defined in the specification named IDD4. The increase in the current consumed in the read/write operations may cause power noise and unwanted effects in the semiconductor memory device.
Therefore, a non-precharge scheme where the input/output lines are not precharged is used to reduce such current in a Dynamic Random Access Memory (DRAM) device. In this case, a precharge operation is not performed during a write operation section, and the local input/output (LIO) lines are precharged in order to perform another command operation after the write operation is completed. As a result, the voltage or current level of the internal data lines changes drastically in a short amount of time resulting in potential damage and decreased stability.